ETH0 LWIP Echo Server Test

Create Vivado Project

Modify the parameters based on the previous Vivado project according to the schematic:

Schematic:

Vivado parameter modification:

The pins for Ethernet0 are already fixed to the MIO pins on the PS side in the schematic: MIO16~MIO27.

Check MDIO, which is used for Ethernet communication (MDIO (Management Data Input/Output) is an interface protocol for managing Ethernet Physical Layer (PHY) chips). MDIO corresponds to MIO52 and MIO53.

After completing the parameter configuration, click OK. The Block Design (BD) is as follows:

Similarly, perform the subsequent operations to generate a new .xsa file:

Create Vitis Application Project

Similarly, first update by clicking Update Hardware Specification. Select the .xsa file path. When the following dialog box appears, click OK, which indicates the update was successful.

Modify the platform's BSP file: add the lwip library. Although there are two Board Support Packages, you must modify the one shown below. Modifying the other one will cause an error when creating the application project. Finally, click OK.

After the modification, be sure to right-click the platform project and select Build Project. If you do not rebuild, creating the application project later will also result in an error.

Create the application project. The only difference is selecting the lwIP Echo Server template:

You can modify the IP address as needed (this should be the IP address of the development board).

For example, if the computer's IP is on the 192.168.3 subnet, you must modify the IP address and gateway in the code to be on the same 192.168.3 subnet to allow the server and client to ping each other:

Modify LWIP to support RTL8211F

In the hardware design of V1.1.0, the PHY chip for the Ethernet interface has been replaced from RTL8211E to RTL8211F. Currently, the LWIP driver provided in vitis does not support RTL8211F, so it is necessary to modify the source code of LWIP accordingly.

The file that needs to be modified is C:\Xilinx\Vitis\2021.1\data\embeddedsw\ThirdParty\sw_services\lwip211_v1_5\src\contrib\ports\xilinx\netif\xemacpsif_physpeed.c

x
// Add RTL8211F macro definition.
#define PHY_REALTEK_RTL8211E                0xC915
#define PHY_REALTEK_RTL8211F                0xC916

#define RTL8211F_PAGSR              (0x1f)
#define RTL8211F_PHYSR              (0x1a)
#define RTL8211F_MIICR              (0x11)
#define RTL8211F_PHYSR_PAGE         (0xa43)
#define RTL8211F_MIICR_PAGE         (0xd08)
#define RTL8211F_PHYSR_LINK_MASK    (0x0004)
#define RTL8211F_PHYSR_SPEED_MASK   (0x0030)
#define RTL8211F_PHYSR_1000         (0x0020)
#define RTL8211F_PHYSR_100          (0x0010)
#define RTL8211F_PHYSR_10           (0x0000)
#define RTL8211F_TXDLY_MASK         (0x01<<8)

// Modified the get_Realtek_phy_speed function to support RTL8211F.
static u32_t get_Realtek_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
{
    ...
    u16_t phy_identity2 = 0;
    ...
    
    xil_printf("autonegotiation complete \r\n");

    //Identify PHY model
    XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG,
                    &phy_identity2);

    switch (phy_identity2)
    {
        case PHY_REALTEK_RTL8211F:
        {
            xil_printf("detected RTL8211F \r\n");
            //Switch to page 0xd08
            XEmacPs_PhyWrite(xemacpsp, phy_addr, RTL8211F_PAGSR, RTL8211F_MIICR_PAGE);
            // enable TXDLY
            XEmacPs_PhyRead(xemacpsp, phy_addr, RTL8211F_MIICR, &control);
            XEmacPs_PhyWrite(xemacpsp, phy_addr, RTL8211F_MIICR, control | RTL8211F_TXDLY_MASK);

            //Switch to page 0xA43
            XEmacPs_PhyWrite(xemacpsp, phy_addr, RTL8211F_PAGSR, RTL8211F_PHYSR_PAGE);
            XEmacPs_PhyRead(xemacpsp, phy_addr, RTL8211F_PHYSR, &status_speed);
            //Switch back to default page
            XEmacPs_PhyWrite(xemacpsp, phy_addr, RTL8211F_PAGSR, 0);
            //If there is link
            if (status_speed & RTL8211F_PHYSR_LINK_MASK) {
                temp_speed = status_speed & RTL8211F_PHYSR_SPEED_MASK;

                if (temp_speed == RTL8211F_PHYSR_1000)
                    return 1000;
                else if(temp_speed == RTL8211F_PHYSR_100)
                    return 100;
                else
                    return 10;
            }
            break;
        }
        case PHY_REALTEK_RTL8211E:
            xil_printf("detected RTL8211E \r\n");
            //RTL8211E fall-back to default Realtek behaviour
        default:
        {
            XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
                            &status_speed);
            if (status_speed & 0x400) {
                temp_speed = status_speed & IEEE_SPEED_MASK;

                if (temp_speed == IEEE_SPEED_1000)
                    return 1000;
                else if(temp_speed == IEEE_SPEED_100)
                    return 100;
                else
                    return 10;
            }
            break;
        }
    }
    return XST_FAILURE;
}

After making the changes, restart the Vitis process and recompile the platform project.

You can also download the modified lwip compressed package from GitHub.

Compile and Debug

After the project compiles successfully, connect the development board's JTAG to the computer with a Type-C USB cable, and use another Type-C USB cable to connect the board's PS UART to the computer. Connect the board to the computer with an Ethernet cable. On the computer, open a serial terminal tool like MobaXterm and establish a connection with the board's PS UART. After powering on, you can observe through the serial port that the network has started, the IP address is 192.168.3.150, and the service port is 7.

Ping this IP address from the computer. A successful ping indicates that the network connection is established:

After connecting to the development board's server using a network debugging tool on your computer, any data you send to the board will be echoed back. (Set the port number to 7 and use the IP address obtained from the serial port output).